ucbus-stepper-log.md

// sequence like
// S: 1 2 3 4 5 6 7 8
// A: ^ ^ ^ x v v v x
// B: ^ x v v v x ^ ^
// sine, 0-1022 (511 center / 'zero'), 256 steps
uint16_t LUT[256] = {
    511,524,536,549,561,574,586,598,611,623,635,647,659,671,683,695,
    707,718,729,741,752,763,774,784,795,805,815,825,835,845,854,863,
    872,881,890,898,906,914,921,929,936,943,949,956,962,967,973,978,
    983,988,992,996,1000,1003,1007,1010,1012,1014,1016,1018,1020,1021,1021,1022,
    1022,1022,1021,1021,1020,1018,1016,1014,1012,1010,1007,1003,1000,996,992,988,
    983,978,973,967,962,956,949,943,936,929,921,914,906,898,890,881,
    872,863,854,845,835,825,815,805,795,784,774,763,752,741,729,718,
    707,695,683,671,659,647,635,623,611,598,586,574,561,549,536,524,
    511,498,486,473,461,448,436,424,411,399,387,375,363,351,339,327,
    315,304,293,281,270,259,248,238,227,217,207,197,187,177,168,159,
    150,141,132,124,116,108,101,93,86,79,73,66,60,55,49,44,
    39,34,30,26,22,19,15,12,10,8,6,4,2,1,1,0,
    0,0,1,1,2,4,6,8,10,12,15,19,22,26,30,34,
    39,44,49,55,60,66,73,79,86,93,101,108,116,124,132,141,
    150,159,168,177,187,197,207,217,227,238,248,259,270,281,293,304,
    315,327,339,351,363,375,387,399,411,424,436,448,461,473,486,498,
};
void STEP_A4950::init(){
    // all of 'em, outputs
    AIN1_PORT.DIRSET.reg = AIN1_BM;
    AIN2_PORT.DIRSET.reg = AIN2_BM;
    BIN1_PORT.DIRSET.reg = BIN1_BM;
    BIN2_PORT.DIRSET.reg = BIN2_BM;
    // transform full sine table for DAC table
    // i.e. rectify...
    for(uint16_t i = 0; i < 256; i ++){
        if(LUT[i] > 511){
            dacLUT[i] = (LUT[i] - 511) * C_SCALE;
        } else if (LUT[i] < 511){
            dacLUT[i] = abs(511 - LUT[i]) * C_SCALE;
        } else {
            dacLUT[i] = 0;
        }
    }
    // start condition,
    step();
}
void STEP_A4950::step(void){
    // increment: wrapping comes for free with uint8_t
    if(_dir){
        _aStep ++;
        _bStep ++;
    } else {
        _aStep --;
        _bStep --;
    }
    // a phase,
    if(LUT[_aStep] > 511){
        A_UP;
    } else if (LUT[_aStep] < 511){
        A_DOWN;
    } else {
        A_OFF;
    }
    // a DAC
    dacs->writeDac0(dacLUT[_aStep]);
    // b phase,
    if(LUT[_bStep] > 511){
        B_UP;
    } else if (LUT[_bStep] < 511){
        B_DOWN;
    } else {
        B_OFF;
    }
    // b DAC
    dacs->writeDac1(dacLUT[_bStep]);
}