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Commit 880b2451 authored by Jake Read's avatar Jake Read
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reorg

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...@@ -70,7 +70,7 @@ Things to try would include... taking the Ethernet library offline (into-repo) a ...@@ -70,7 +70,7 @@ Things to try would include... taking the Ethernet library offline (into-repo) a
So, for quicksies, and to settle this current debate, I should try not-pinging with this code, just straight up receiving hella UDP upstream... So, for quicksies, and to settle this current debate, I should try not-pinging with this code, just straight up receiving hella UDP upstream...
### Non-Pining Speed Tests ### Non-Pinging Speed Tests
- setup Arduino to, after one packet rx (to get an IP to tx-back-to) just free-form wrips packets up north, and occasionally prints rates to the OLED - setup Arduino to, after one packet rx (to get an IP to tx-back-to) just free-form wrips packets up north, and occasionally prints rates to the OLED
- setup an async (?) version of the python inheritor, and collect them data - setup an async (?) version of the python inheritor, and collect them data
...@@ -79,7 +79,19 @@ So... this does improve the rate substantially: ...@@ -79,7 +79,19 @@ So... this does improve the rate substantially:
![oneway](images/2023-12-28_eth-oneway-64.png) ![oneway](images/2023-12-28_eth-oneway-64.png)
I think actually these are blocking calls, so flow-control down below is as simple as running the thing over-and-over: I am seeing on the scope that each transmit takes about 350us, which is reflected in the histogram above... so, while I am also wondering how much of this is to do with the ethernet-to-usb adapter I am using on the laptop side, I am basically convinced that the bottleneck here is the 12MHz SPI.
However, that would mean we have ~ 10/12 MBits/sec of overhead. But, also looking at the scope, I see significant air gaps between each byte on the SPI line, around 2us per byte - meaning that this is not entirely unlikely (each byte is just 0.8us-ish) so we already have 2/3rds overhead just in those air gaps, and then we have also whatever WIZ-To-Micro overhead to contend with as well.
So, scope trace: blue arrows highlight the length of one packet-write in embedded, with SPI transactions on CH2 (CS) and CH3 (CLK) - this shows me it's blocking writes, basically, and the width of the write is essentially the same as we measure in the histogram above.
![spi](images/2023-12-28_ethernet-wiz-spi-01.jpg)
Then we zoom in to see all of these "air gaps" in the SPI CLK line (CH3) - no data is transferred without a CLK pulse, so, this is big overhead loss, and IDK WTF the MCU is doing in these gaps, but it ain't efficient.
![spi](images/2023-12-28_ethernet-wiz-spi-02.jpg)
This is the relevant CPP and Python...
```cpp ```cpp
void loop() { void loop() {
......
wiznet_ethernet/images/2023-12-28_ethernet-wiz-spi-01.jpg

659 KiB

wiznet_ethernet/images/2023-12-28_ethernet-wiz-spi-02.jpg

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